Array substrate, method of manufacturing the array substrate, and liquid crystal display device having the array substrate

ABSTRACT

In an array substrate, a method of manufacturing the array substrate, and a liquid crystal display (LCD) device having the array substrate, a pixel electrode includes an outline portion, connection portions, and slit portions. The outline portion is arranged toward a data line and a gate line thereon, and the connection portions extend in a direction that crosses the data line and the gate line, respectively, to connect to the outline portion. The slit portions protrude from side surfaces of the connection portions to connect to the outline portion. A shielding electrode is arranged toward the outline portion between the data line and the outline portion, and the gate line and the outline portion.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. application Ser. No.12/413,149, filed on Mar. 27, 2009. This application claims priorityfrom and the benefit of Korean Patent Application No. 10-2008-0073647,filed on Jul. 28, 2008, which is hereby incorporated by reference forall purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an array substrate, a method ofmanufacturing the array substrate, and a liquid crystal display (LCD)device having the array substrate. More particularly, exemplaryembodiments of the present invention relate to array substrate having animproved display quality, a method of manufacturing the array substrate,and an LCD device having the array substrate.

2. Discussion of the Background

An LCD device of a mobile patterned vertical alignment (mPVA) mode(hereinafter, an mPVA LCD device) may have an optical mode, in whichcircular polarization is applied, and in which the transmissivity isrelatively superior to other modes.

The mPVA LCD device having the circular polarization optical mode mayhave disadvantages related to viewing properties or contrast ratiocompared to a PVA mode in which to linear polarization is applied.However, the transmissivity of the linear polarization PVA mode may belower than the transmissivity of the circular polarization PVA mode.

Thus, when a linear polarization optical mode is applicable to an mPVAmode, the aperture ratio of a pixel may be large, and a liquid crystaldirector may form an angle of about 45 degrees with respect to thepolarization axis of a polarizer, in order to improve transmissivity.

However, the linear polarization mPVA mode liquid crystal is controlledby a fringe field when a slit portion is formed on a common electrode ofa color filter substrate. Accordingly, the linear polarization mPVA modeis disadvantageous in that transmissivity may be reduced.

To overcome these problems, a micro-slit mode, in which a slit is formedon a pixel electrode of an array substrate, rather than on the commonelectrode, may be used. However, the micro-slit mode is disadvantageousin that controlling the liquid crystal at edges of micro-slits orbetween the micro-slits formed on the pixel electrode is difficult, andthe LCD device display quality may be deteriorated thereby.

SUMMARY OF THE INVENTION

The present invention provides an array substrate having an improveddisplay quality.

The present invention also provides a method of manufacturing theabove-mentioned array substrate.

The present invention also provides a liquid crystal display (LCD)device having the above-mentioned array substrate.

Additional features of the invention will be set forth in thedescription which follows, and in part will be apparent from thedescription, or may be learned by practice of the invention.

The present invention discloses an array substrate including asubstrate, a pixel electrode, and a shielding electrode. The substrateincludes a gate line and a data line that cross each other and that areinsulated from each other, and a switching element connected to the gateline and the data line arranged thereon. The pixel electrode includes anoutline portion, a plurality of connection portions, and a plurality ofslit portions. The outline portion is arranged on the substrate alongthe data line and the gate line. The connection portions extend in acrossing direction of the data line and a crossing direction of the gateline, and connect to the outline portion. The connection portions dividea pixel area defined by the outline portion into a plurality of domains.The slit portions protrude from side surfaces of the connection portionsin each of the domains, and the slit portions connect to the outlineportion. The shielding electrode is arranged along the outline portionson the data line and the outline portions on the gate line to shield thedata line and the gate line, respectively. The shielding electrode isarranged between the data line and the outline portion.

The present invention discloses a method of manufacturing an arraysubstrate including forming a switching element, a pixel electrode, anda shielding electrode on a substrate. The switching element is connectedto a gate line and a data line. The pixel electrode includes an outlineportion formed on the substrate along the data line and the gate line, aplurality of connection portions dividing a pixel area, which aredefined by the outline portion, into a plurality of domains. The pixelarea extends in a crossing direction of the data line and a crossingdirection of the gate line and connects to the outline portion, theconnection portions, and a plurality of slit portions that protrude fromside surfaces of the connection portions in each of the domains, inwhich the slit portions are connected to the outline portion. Ashielding electrode is formed along the outline portion on the data lineand the outline portion on the gate line to shield the data line and thegate line, respectively, and is disposed between the data line and theoutline portion.

The present invention discloses an LCD device including a firstsubstrate, a second substrate, and a liquid crystal layer. The firstsubstrate includes an upper substrate and a common electrode. The secondsubstrate includes a lower substrate, a pixel electrode, and a shieldingelectrode. The lower substrate has a switching element connected to agate line, and a data line arranged thereon. The pixel electrodeincludes an outline portion, connection portions, and slit portions. Theoutline portion is arranged along the data line and the gate linethereon. The connection portions extend in a direction that crosses thedata line and the gate line, respectively, to connect to the outlineportion. The slit portions protrude from side surfaces of the connectionportions to connect to the outline portion. The shielding electrode isarranged along the outline portion on the data line and the outlineportion on the gate line to shield the data line and the gate line,respectively, and is arranged between the data line and the outlineportion. The liquid crystal layer is disposed between the pixelelectrode and the common electrode.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and areintended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The patent or application file contains at least one drawing executed incolor. Copies of this patent or patent application publication withcolor drawing(s) will be provided by the Office upon request and paymentof the necessary fee.

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this specification, illustrate embodiments of the invention, andtogether with the description serve to explain the principles of theinvention.

FIG. 1 is a plan view showing a liquid crystal display (LCD) deviceaccording to an exemplary embodiment of the present invention.

FIG. 2 is an enlarged plan view showing an example of a pixel area shownas FIG. 1.

FIG. 3 is a cross-sectional view taken along line I-I′ in FIG. 2.

FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D, FIG. 4E, FIG. 4F, FIG. 4G, FIG. 4H,and FIG. 4I are cross-sectional views showing a process formanufacturing the array substrate shown in FIG. 1, FIG. 2, and FIG. 3.

FIG. 5A is a cross-sectional view taken along line II-II′ in FIG. 2.

FIG. 5B is a cross-sectional view taken along line III-III′ in FIG. 2.

FIG. 6 is a cross-sectional view showing movements of a liquid crystallayer between the shielding electrode and the outline portion of a pixelelectrode in FIG. 5A and FIG. 5B.

FIG. 7A is an image observing light transmissivity of the LCD device inwhich slit portions are formed in a diagonal direction.

FIG. 7B is an image observing light transmissivity of the LCD deviceshown as FIG. 1, FIG. 2, FIG. 3, FIG. 4, FIG. 5A, and FIG. 5B.

FIG. 8 is a graph representing response time of LCD devices shown asFIG. 7A and FIG. 7B;

FIG. 9 is an enlarged plan view showing a pixel area of the arraysubstrate of the LCD device according to another exemplary embodiment ofthe present invention.

FIG. 10 is a cross-sectional view taken along line IV-IV′ in FIG. 9.

FIG. 11A, FIG. 11B, FIG. 11C, and FIG. 11D are cross-sectional viewsshowing a process for manufacturing the array substrate shown in FIG. 9and FIG. 10.

FIG. 12A is an image showing light transmissivity of the LCD devicehaving an array substrate identical to the array substrate shown as FIG.9 and FIG. 10 except that a pixel electrode does not have an outlineportion.

FIG. 12B is an image showing light transmissivity of the LCD devicehaving the array substrate shown in FIG. 9 and FIG. 10.

FIG. 13 is a graph showing a response time of the LCD devices shown inFIG. 12A and FIG. 12B.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

The present invention is described more fully hereinafter with referenceto the accompanying drawings, in which example embodiments of thepresent invention are shown. The present invention may, however, beembodied in many different forms and should not be construed as limitedto the example embodiments set forth herein. Rather, these exampleembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the present invention tothose skilled in the art. In the drawings, the sizes and relative sizesof layers and regions may be exaggerated for clarity.

It will be understood that when an element or layer is referred to asbeing “on,” “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present. Like numerals refer to likeelements throughout. As used herein, the term “and/or” includes any andall combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the teachings of the present invention.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as shown in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularexemplary embodiments only and is not intended to be limiting of thepresent invention. As used herein, the singular forms “a,” “an” and“the” are intended to include the plural forms as well, unless thecontext clearly indicates otherwise. It will be further understood thatthe terms “comprises” and/or “comprising,” when used in thisspecification, specify the presence of stated features, integers, steps,operations, elements, and/or components, but do not preclude thepresence or addition of one or more other features, integers, steps,operations, elements, components, and/or groups thereof.

Exemplary embodiments of the invention are described herein withreference to cross-sectional illustrations that are schematicillustrations of idealized example embodiments (and intermediatestructures) of the present invention. As such, variations from theshapes of the illustrations as a result, for example, of manufacturingtechniques and/or tolerances, are to be expected. Thus, exemplaryembodiments of the present invention should not be construed as limitedto the particular shapes of regions shown herein but are to includedeviations in shapes that result, for example, from manufacturing. Forexample, an implanted region shown as a rectangle will, typically, haverounded or curved features and/or a gradient of implant concentration atits edges rather than a binary change from implanted to non-implantedregion. Likewise, a buried region formed by implantation may result insome implantation in the region between the buried region and thesurface through which the implantation takes place. Thus, the regionsshown in the figures are schematic in nature and their shapes are notintended to show the actual shape of a region of a device and are notintended to limit the scope of the present invention.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

Hereinafter, the present invention will be explained in detail withreference to the accompanying drawings.

FIG. 1 is a plan view showing a liquid crystal display (LCD) device 100according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the LCD device 100 according to an exemplaryembodiment of the present invention includes a display panel 10 and adriving part 5.

The display panel 10 includes an array substrate 101, an oppositesubstrate 105, and a liquid crystal layer. The array substrate 101 andthe opposite substrate 105 opposite to each other are joined by asealing member 102 having a frame shape. Liquid crystals are disposed inthe space between the array substrate 101, the opposite substrate 105,and the sealing member 102 to form the liquid crystal layer.

The opposite substrate 105 is disposed in a direction from the ground,and the array substrate 101 is disposed in a direction toward the groundin FIG. 1.

The opposite substrate 105 may be a color filter substrate having an RGBcolor filter. The array substrate 101 is an element substrate beingdriven through an active matrix driving process using a thin-filmtransistor (TFT) element.

In addition, the array substrate 101 includes a pixel electrode having amicro-slit pattern formed therethrough in the LCD device 100, and theopposite substrate 105 includes a common electrode having a plate shapeformed therethrough.

The array substrate 101 may have a substantially rectangular shape. Inthis embodiment, a horizontal direction of the array substrate 101 isdefined as ‘x’, and a vertical direction of the array substrate 101 isdefined as ‘y’.

FIG. 2 is an enlarged plan view showing an example of a pixel area shownas FIG. 1. FIG. 3 is a cross-sectional view taken along line I-I′ inFIG. 2.

Referring to FIG. 1, FIG. 2, FIG. 3, a display device 100 includes anarray substrate 101, an opposite substrate 105, and a liquid crystallayer 107.

A plan view of the array substrate 101 is shown in FIG. 2, and across-sectional view of the array substrate 101, the opposite substrate105, and the liquid crystal layer 107 is shown in FIG. 3.

Referring to FIG. 1, FIG. 2, and FIG. 3, the array substrate 101according to the present invention includes a lower substrate 102, aplurality of gate lines 111, a plurality of data lines 115, a switchingelement 108, a shielding electrode 160, and a pixel electrode 170.

FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D, FIG. 4E, FIG. 4F, FIG. 4G, FIG. 4H,and FIG. 4I are cross-sectional views showing a process formanufacturing the array substrate 101 as shown in FIG. 1, FIG. 2, andFIG. 3.

According to a process for manufacturing an array substrate in thisexemplary embodiment, a gate metal, which may be a two-layer structureformed of aluminum (Al) and molybdenum (Mo), is deposited to a thicknessof about 3,000 Å via a sputtering process on the lower substrate 102, anetching process is performed as shown in FIG. 4A to form the gate lines111 and the gate electrode 112 protruded from the gate line 111. Thegate lines 111 are parallel with the horizontal direction to be extendedon the lower substrate 102.

Then, a gate insulation layer 113 and a semiconductor pattern 114 areformed as shown in FIG. 3 and FIG. 4B. The gate insulation layer 113,which may be formed of silicon nitride (SiNx), is deposited to have athickness of about 4,500 Å on the gate lines 111. A semiconductor layer,which may be made of amorphous silicon (n+ a-Si), is deposited to athickness of about 2,000 Å on the gate insulation layer 113, and anamorphous silicon (n+ a-Si) layer doped at a high concentration isdeposited to a thickness of about 500 Å on the gate insulation layer113. The amorphous silicon (n+ a-Si) layers are etched to form asemiconductor pattern 114. The semiconductor pattern 114 is formed onthe gate insulation layer 113 on a location corresponding to the gateelectrode 112.

As shown in FIG. 3 and FIG. 4C, a data metal, which may be a three-layerstructure formed of molybdenum-aluminum-molybdenum, is deposited to athickness of about 300 Å, 2,500 Å, and 1,000 Å, respectively, on thegate insulation layer 113, and is patterned to form the data line 115,the source electrode 121, and the drain electrode 123.

The data lines 115 extend in the vertical direction ‘y’ on the gateinsulation layer 113. The source electrode 121 protrudes from the dataline 115 near the point where the gate line 111 crosses the data line115, to extend on the semiconductor pattern 114 on the gate electrode112. The drain electrode 123 is disposed on the semiconductor pattern114 opposite to the source electrode 121, and extends on the gateinsulation layer 113 in a portion of a pixel area PA .

In this exemplary embodiment, the pixel area PA has a substantiallyrectangular shape that extends in the vertical direction. Alternatively,the pixel area PA may have a Z-shape, such that the gate line 111 isarranged in the horizontal direction around the pixel area PA, and thedata line 115 is arranged in the vertical direction around the pixelarea PA.

When the semiconductor layer and the data metal layer are etched by asingle etching process, the semiconductor pattern 114 is formed belowthe data line 115, the source electrode 121, and the drain electrode123, and is formed on the gate line 112 on the gate insulation layer113. A channel region, which is disposed between the source electrode121 and the drain electrode 123, is formed semiconductor pattern 114using an etch-back process.

The gate electrode 112, the gate insulation layer 113, the semiconductorpattern 114, the source electrode 121, and the drain electrode 123compose a switching element 108.

Then, as shown in FIG. 4D, a first passivation layer 130 covering thelower substrate 102 having the data line 115 formed thereon is formed.The first passivation layer 130, which may be made of silicon nitride(SiNx), may be deposited to a thickness of about 2,000 Å. A contact holemay be formed in the first passivation layer 130 to expose a portion ofthe drain electrode 123.

As shown in FIG. 4E, an organic insulation layer 140 is formed to athickness of about 2.0 μm on the first passivation layer 130. A contacthole 143 exposing a portion of the drain electrode 123 may be formed inthe organic insulation layer 140 and the first passivation layer 130.The organic insulation layer 140 reduces a parasitic capacitance betweena pixel electrode 170, which will be described below, and the data line115. When the pixel electrode 170 is formed to not overlap with the dataline 115, the organic insulation layer 140 may be omitted.

As shown in FIG. 4F, the shielding electrode 160 is formed on theorganic insulation layer 140. The shielding electrode 160 may prevent aparasitic capacitance from forming between the data line 115, the gateline 111, and the pixel electrode 170. Alternatively, the shieldingelectrode 160 may form a storage capacitor with the pixel electrode 170to store a pixel voltage applied to the pixel electrode 170 for oneframe.

An optically transparent and electrically conductive material such asindium tin oxide (ITO) or indium zinc oxide (IZO) is deposited to athickness of about 900 A on the organic insulation layer 140, and ispatterned to form the shielding electrode 160.

FIG. 5A is a cross-sectional view taken along line II-II′ in FIG. 2.FIG. 5B is a cross-sectional view taken along line III-III' in FIG. 2.

Referring to FIG. 2, FIG. 5A, and FIG. 5B, the shielding electrode 160is formed on the gate line 111 and the data line 115 to shield in thewidth direction. That is, the shielding electrode 160 is formed on thegate line 111 between the pixel areas PA and the data line 115, and aline width of the shielding electrode 160 is wider than that of the gateline 111 and the data line 115, respectively. Thus, the shieldingelectrode 160 extends to an edge of the pixel area PA. In this exemplaryembodiment, the shielding electrode 160 is formed from the opticallytransparent and electrically conductive material so that an apertureratio of the pixel area PA is not reduced even if the shieldingelectrode 160 overlaps with an edge of the pixel area PA.

As shown in FIG. 4G, a second passivation layer 165 is formed on theshielding electrode 160. The second passivation 165 layer may be formedof a material and a thickness substantially identical to the firstpassivation layer 130. A contact hole may be formed in the secondpassivation layer 165, in which the contact hole is connected to acontact hole 143 formed in the organic insulation layer 140.

As shown in FIG. 4H, an optically transparent and electricallyconductive material such as ITO or IZO is deposited to a thickness ofabout 900 Å on the second passivation layer 165, and is patterned toform the pixel electrode 170. The pixel electrode 170 is connected tothe drain electrode 123 through the contact hole 143.

Referring to FIG. 2, FIG. 5A, and FIG. 5B, the pixel electrode 170includes an outline portion 175, a connection portion 171, and a slitportion 173. The outline portion 175 is formed on the second passivationlayer 165 and corresponds to the edge of the pixel area PA along thegate line 111 and the data line 115. A portion of the outline portion175 may be formed to overlap with the shielding electrode 160 thatextends to the edge of the pixel area PA in the width direction. Asshown in FIG. 5A and FIG. 5B, a portion of the outline portion 175 maybe formed to overlap with the gate line 111 and the data line 115 in thewidth direction.

The connection portions 171 divide the pixel area PA into a plurality ofdomains to connect to the outline portion 175. The connection portions171 are disposed in a direction crossing an extending direction of thegate line 111 and the data line 115, respectively.

In this exemplary embodiment, as shown in FIG. 2, the pixel electrode170 includes two of the connection portions 171. One connection portion171 is disposed in a direction at an angle of 45 degrees with respect tothe gate line 111, and another connection portion 171 is disposed in adirection at an angle of 135 degrees with respect to the gate line 111.

Two of the connection portions 171 extend to diagonal directions of thepixel electrode 170, respectively. Thus, the connection portions 171 aredisposed in an X-shape. Accordingly, the pixel area PA is divided intoeight domains by the connection portions 171.

The slit portions 173 are parallel with each other on the pixel area PAdomains, respectively. The slit portions 173 protrude from side surfacesof the connection portion 171 to connect to the outline portion 175. Theslit portions 173 are substantially parallel with the data line 115 on adomain contacting the gate line 111, and the slit portions 173 aresubstantially parallel with the gate line 111 on a domain contacting thedata line 115.

In this exemplary embodiment, two pixel electrodes 170 are disposed onone pixel area PA. Two pixel electrodes 170 are disposed on the dataline 115 to connect to each other through the outline portion 175. Thus,the length of the horizontal direction and the length of the verticaldirection of the pixel electrode 170 are almost identical to each other.Accordingly, the length of the horizontal direction and the length ofthe vertical direction of the slit portions 173 are almost identical toeach other.

When a data signal is applied from the driving part 5 to the data line115, and a gate signal is applied to the gate line 111, the data signalis applied to the pixel electrode 170 via the switching element 108 as apixel voltage.

In this exemplary embodiment, a portion of the outline portion 175 ofthe pixel electrode 170 overlaps with the data line 115 and the gate111, but the shielding electrode 160 forms a parasitic capacitance withthe data line 115 and prevents a parasitic capacitance from being formedbetween the pixel electrode 170 and the data line 115, thus preventing adistorted data signal. .

Finally, as shown in FIG. 4I a lower alignment layer 168 covering thepixel electrode 170 is formed.

The lower alignment layer 168 and the opposite substrate 105, which willbe described below, make liquid crystal molecules of the liquid crystallayer 107 align in a perpendicular direction. That is, the liquidcrystal molecules are aligned in the direction from the array substrate101 toward the opposite substrate 105 in a first stage.

The array substrate may further include a lower polarizer 30. As shownin FIG. 4I the lower polarizer 30 is attached on the lower substrate 102to be manufactured in the array substrate 101.

The lower polarization axis of the lower polarizer 30 is parallel withextending directions of the connection portions 171, that is, diagonaldirections. Accordingly, the lower polarization axis is disposed in adirection at an angle of about 45 degrees or about 135 degrees withrespect to the extending direction of the slit portion 173.

Referring to FIG. 1, FIG. 2, and FIG. 3, the opposite substrate 105 mayinclude an upper substrate 104, a light-blocking pattern 181, a colorfilter pattern 185, an overcoating layer 187, a common electrode 190, anupper alignment layer 60, and an upper polarizer 70.

The light-blocking pattern 181 is formed below the upper substrate 104in correspondence with the gate line 111, the data line 115, and theswitching element 108. Thus, a color filter pattern 185 is formed on theupper substrate corresponding to the pixel area PA. A color filterpattern 185 may include, for example, a red filter, a green filter, anda blue filter. The red filter, the green filter, and the blue filter maybe disposed in order on each pixel area PA in the horizontal directionx.

The overcoating layer 187 covers the color pattern 185 and thelight-blocking pattern 181, and the common electrode 190 is formed onthe overcoating layer 187.

The upper alignment layer 60 is formed on the common electrode 190 tovertically align a liquid crystal layer 107.

The upper polarizer 70 is attached on the upper substrate 104, and apolarization axis of the upper polarizer 70 may be substantiallyperpendicular to a polarization axis of the lower polarizer 30.

In this exemplary embodiment, where micro-slit patterns such as the slitportions 173 are formed in the pixel electrode 170, a vertically alignedliquid crystal is used. Thus, a plurality of domains may be formed inthe pixel area PA so that side viewing properties of the LCD device 100may be improved.

FIG. 6 is a cross-sectional view showing movements of liquid crystallayer between the shielding electrode and the outline portion of a pixelelectrode in FIG. 5A or FIG. 5B.

Referring to FIG. 6, when the pixel voltage is applied to the pixelelectrode 170, an electric field boundary is formed between theshielding electrode 160 and the outline portion 175. An edge of theoutline portion 175 overlaps with an upper portion of the shieldingelectrode 160 so that a horizontal component of the electric fieldboundary is formed stronger than that of an electric field boundary ofthe other portion. Thus, as shown in FIG. 6, it is recognized that adirection of liquid crystal molecules on the shielding electrode 160 isclose to a horizontal direction.

That is, a second efficiency of liquid crystal molecules is increased ina condition where an electric field is applied, in which the liquidcrystal molecules are placed at an edge of the pixel area PA. The secondefficiency means a movement efficiency in which the liquid crystalmolecules are rotated from a vertical direction to a horizontaldirection.

Alternatively, a horizontal component of the electric field boundary maybe substantially parallel with a vertical direction at an upper portionof the gate line 111, and may be substantially parallel with ahorizontal direction at an upper portion of the data line 115. Also, adirector of the liquid crystal molecules may be arranged in parallelwith a length direction of the slit portions 173. The slit portions 173are extended to the horizontal direction or the vertical directiondepending on the domain.

That is, a horizontal component direction of the electric field boundaryin which the liquid crystal molecules move is substantially the same asa length direction of the slit portion 173, which guides the director ofthe liquid crystal molecules. Thus, the liquid crystal molecules do notneed to rotate in a horizontal direction. Accordingly, a thirdefficiency of the liquid crystal molecules is increased. The thirdefficiency means a rotation efficiency of the liquid crystal moleculesin the horizontal direction.

Accordingly, the liquid crystal molecules may be effectively controlledat the edge of the pixel area PA so that texture generation isprevented, and the aperture ratio and response time of the liquidcrystal molecules may be improved.

FIG. 7A is an image showing light transmissivity of the LCD device inwhich slit portions 173 are formed in diagonal directions. FIG. 7B is animage showing light to transmissivity of the LCD device 100 shown asFIG. 1, FIG. 2, FIG. 3, FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D, FIG. 4E,FIG. 4F, FIG. 4G, FIG. 4H, FIG. 4I, FIG. 5A, and FIG. 5B.

FIG. 7A and FIG. 7B are images showing light transmissivity after anidentical time from that when the pixel voltage is applied. A darkportion of the images represents that light transmissivity is lower thanother portions due to a slow response of liquid crystal molecules.

As shown in FIG. 7A, the slit portion 173 of the LCD device is extendedto one of the diagonal directions unlike in the present exemplaryembodiment. In addition, the outline portion 175 connecting to edgeportions of the slit portion 173 is removed, a shielding electrode 160as light-blocking metal is formed on a portion of the pixel area PAunlike in the present exemplary embodiment. The LCD device issubstantially identical to the LCD device 100 of the present exemplaryembodiment except in the-above mentioned manner.

The image in FIG. 7B is brighter than the image in FIG. 7A, and has auniform luminance. A portion between an edge of the pixel area PA andthe slit portions 173 is relatively darker than the other portion inFIG. 7B.

FIG. 8 is a graph showing a response time of the LCD device shown asFIG. 7A and FIG. 7B.

A horizontal axis represents an elapsed time after applying a pixelvoltage, and a vertical axis represents a light transmissivity of apixel area PA in FIG. 8. Referring to FIG. 8, it is recognized that alight transmissivity of the LCD device described in FIG. 7A, which isrepresented by the dashed line, is substantially lower than lighttransmissivity of the LCD device 100 of the present exemplary embodimentdescribed in FIG. 7B, which is represented by the solid line, for asubstantially identical time.

That is, the LCD device described in FIG. 7A and FIG. 8 does not includethe light transmissivity improving effect by the outline portion 175 andthe shielding electrode 160 unlike the present exemplary embodiment, anda direction of the slit portion 173 and a direction of horizontalelectric field is different from each other in an angle of 45 degrees sothat the second and third efficiency of the liquid crystal molecules islow.

The second and third efficiency of the liquid crystal molecules in theLCD device 100 of the present exemplary embodiment may be improved bythe outline portion 175, the shielding electrode 160, and a direction ofthe slit portion 173 more than the LCD device described in FIG. 7A andFIG. 8, so that the display quality of the LCD device 100 may beimproved.

FIG. 9 is an enlarged plan view showing a pixel area of the arraysubstrate of the LCD device according to another exemplary embodiment ofthe present invention. FIG. 10 is a cross-sectional view taken alongline IV-IV' in FIG. 9.

Referring to FIG. 9 and FIG. 10, an array substrate and a process formanufacturing the array substrate of this exemplary embodiment issubstantially identical to the array substrate and the process formanufacturing the array substrate described in FIG. 1 and FIG. 6, excepta size of the pixel electrode 370 and an omitted organic insulationlayer 140. Accordingly, the same reference numerals will be used torefer to the same elements as those described, and any detailedexplanation will be omitted.

In this exemplary embodiment, wherein the one pixel electrode 370 isdisposed in the pixel area PA, and a long side of the pixel electrode370 is substantially parallel with the direction in which the data line315 extends. The pixel electrode is substantially identical to the pixelelectrode 170 described in FIG. 1, FIG. 2, FIG. 3, FIG. 4A, FIG. 4B,FIG. 4C, FIG. 4D, FIG. 4E, FIG. 4F, FIG. 4G, FIG. 4H, FIG. 4I, FIG. 5A,FIG. 5B, and FIG. 6. Thus, the slit portions 373 of the verticaldirection are longer than the slit portions 373 of the horizontaldirection.

FIG. 11A, FIG. 11B, FIG. 11C, and FIG. 11D are cross-sectional viewsshowing a process for manufacturing the array substrate shown as FIG. 9and FIG. 10.

In a process for forming the array substrate according to this exemplaryembodiment, the organic insulation layer 140 is omitted, and a firstpassivation layer 330 is formed as shown in FIG. 11A, and a shieldingelectrode 360 is formed on the first passivation layer 330 as shown inFIG. 11B. Then, a second passivation layer 365 covering the shieldingelectrode 360 is formed as shown in FIG. 11C. Then, the pixel electrode370 is formed on the second passivation layer 365 and an alignment layer368 is formed as shown in FIG. 11D.

A process for forming an organic insulation layer 140 is omitted toreduce a process step in this exemplary embodiment.

The LCD device in this exemplary embodiment is substantially identicalto the LCD device described in FIG. 1, FIG. 2, FIG. 3, FIG. 4A, FIG. 4B,FIG. 4C, FIG. 4D, FIG. 4E, FIG. 4F, FIG. 4G, FIG. 4H, FIG. 4I, FIG. 5A,FIG. 5B, and FIG. 6 except having the array substrate in FIG. 9 and FIG.10. Accordingly, any detailed explanation will be omitted.

FIG. 12A is an image showing light transmissivity of the LCD devicehaving an array substrate identical to the array substrate shown as FIG.9 and FIG. 10, except that a pixel electrode does not have an outlineportion. FIG. 12B is an image showing light transmissivity of the LCDdevice having the array substrate shown as FIG. 9 and FIG. 10.

An outline portion 375 connecting to edge portions of the slit portion373 is removed, and a shielding electrode 360 as light-blocking metal isformed on a portion of the io pixel area PA, unlike in the presentexemplary embodiment. The LCD device is substantially identical to theLCD device 100 of the present exemplary embodiment except in the-abovementioned manner. The image in FIG. 12B is brighter than the image inFIG. 12A, and has a uniform luminance. A portion between an edge of thepixel area PA and the slit portions 373 is relatively darker than theother portion in FIG. 12A.

FIG. 13 is a graph representing response time of LCD devices shown asFIG. 12A and FIG. 12B.

A horizontal axis represents an elapsed time after applying a pixelvoltage, and a vertical axis represents a light transmissivity of apixel area PA in FIG. 13. Referring to FIG. 13, it is recognized thatafter 40 msec from applying a pixel voltage a light transmissivity ofthe LCD device described in FIG. 12A, which is represented by the dashedline, is substantially lower than light transmissivity of the LCD deviceof the present exemplary embodiment described in FIG. 12B, which isrepresented by the solid line, for a substantially identical time.

That is, the second and third efficiency of the liquid crystal moleculesin the LCD device of the present exemplary embodiment is remarkablyimproved by the outline portion 375 and the shielding electrode 360 overthe LCD device described in FIG. 12A, thus the display quality of theLCD device may be improved.

It will be apparent to those skilled in the art that variousmodifications and variation can be made in the present invention withoutdeparting from the spirit or scope of the invention. Thus, it isintended that the present invention cover the modifications andvariations of this invention provided they come within the scope of theappended claims and their equivalents.

1. An array substrate comprising: a substrate comprising a gate line anda data line that cross each other and that are insulated from eachother, and a switching element connected to the gate line and the dataline ; a pixel electrode comprising: an outline portion arranged on thesubstrate along the data line and the gate line, a plurality ofconnection portions that extend in a crossing direction of the data lineand the gate line, and connect to the outline portion, the connectionportions dividing a pixel area defined by the outline portion into aplurality of domains, and a plurality of slit portions that protrudefrom side surfaces of the connection portions in each of the domains,the slit portions being connected to the outline portion; and ashielding electrode arranged along the outline portion on the data lineand the outline portion on the gate line and shielding the data line andthe gate line, respectively, wherein the shielding electrode is arrangedbetween the data line and the outline portion.